1. Field of the Invention
The present invention relates to a FIR digital filter which produces a finite impulse response (FIR) based on a finite number of stages of fundamental symmetrical digital filter circuits extendibly and programmably arranged in cascade, and particularly to a FIR digital filter which is efficiently constructed in a configuration adapted for manufacture as a semiconductor integrated circuit.
2. Related Art Statement
In general, the convolution sum behavior of a FIR digital filter can be described by the following equation (1): ##EQU1## where x.sub.n, x.sub.n-1, . . . , x.sub.1 denote an input signal, Y.sub.n denotes an output signal and a.sub.0, a.sub.1, . . . , a.sub.N-1 denote finitely successive degrees or orders of the digital filter, respectively.
The above operation is fundamentally effected by the combination of multiplication, addition and unit delay operations, so that the FIR digital filter can be composed of a combination of multipliers, adders and unit delay elements which are arranged, for instance, as shown in FIG. 1. In the arrangement shown in FIG. 1, 9.sub.1 to 9.sub.n denote multiplication coefficient inputs, 10.sub.1 to 10.sub.n denote mulitpliers, 5.sub.1 to 5.sub.n denote adders and 6.sub.1 and 6.sub.n denote unit delay elements, respectively. With regard to the integrated circuit form of the foregoing FIR digital filter, which was conventionally formed by integrating the fundamental circuit block denoted by the broken line in FIG. 1, it was difficult to realize a large scale integrated circuit (LSI) of the digital filter having low power consumption and high speed operation because of the difficulty of making the required low power, high speed multiplier which has a conventional structure and occupies a small area.
In addition, when the FIR filter is used for the processing of a digital video signal and the like, a symmetrical configuration thereof according to the following equation (2) is frequently employed in general: ##EQU2## where N is an odd number.
When this configuration is employed, a symmetrical FIR digital filter can be realized with about half the number of multipliers required for the configuration shown in FIG. 1.
However, when the above described fundamental circuit configuration shown by the broken line in FIG. 1 is employed, a symmetrical FIR digital filter cannot be effectively realized.
For avoiding the above-mentioned shortcomings, another fundamental symmetrical circuit configuration of the FIR digital filter, shown in FIG. 2, has been proposed. In this fundamental circuit configuration, the required results of multiplication between the input signal and the necessary filter coefficients are previously stored in the read only memory (ROM)4, and then are derived therefrom according to the address defined by the input signal as the occasion demands. Consequently, an efficient symmetrical configuration of the FIR digital filter can be achieved by the cascade connection of this fundamental circuit configuration.
However, the read only memory (ROM) which is customarily employed in the foregoing fundamental circuit configuration has a restricted amount of addressable memory capacity, so that the FIR digital filter formed from such cascaded fundamental circuits has the defect that the number of cascaded stages and the choices of selectable filter coefficients are limited, which limits the filter performance characteristics that can be obtained. This defect can be removed by replacing the read only memory (ROM) with a random access memory (RAM). However, when random access memories are employed for the memories 4 in the cascaded fundamental circuit configurations, a group of data inputs 20 and a group of write signal inputs 7 must also be provided to the memories 4, the numbers of which inputs correspond to the number of bits of the necessary operational data, as shown in FIG. 3 (in which the clock inputs have been omitted for the sake of simplicity). Consequently, another defect is created because the number of connection pins required for the integrated circuit embodiment of the cascaded fundamental circuit configuration is substantially increased, and hence the circuit cannot be realized.
Consequently, in those situations where an extendible and programmable FIR digital filter with a symmetrical configuration is employed for processing a digital video signal, an integrated circuit embodiment thereof having low power consumption and high speed operation cannot be realized, so long as the above described conventional circuit configuration is employed.